Topic
hbm
8 articles
Google's Intel TPU Deal Signals the End of CoWoS Monopoly
Advanced packaging — not wafers — is the binding constraint on AI compute, and Google's reported 3-million-TPU order to Intel is the first crack in TSMC's CoWoS chokehold.
Signal Briefing: June 9, 2026
Nvidia and SK Hynix formalize a multi-year memory co-development pact, locking in next-generation HBM supply as Texas grid stress and drought-zone siting expose the compounding infrastructure risks beneath the AI buildout.
The Memory Wall Is the Inference Wall
DRAM at a 15-year high, HBM5 mockups in Taipei, and Altman calling token costs 'a huge issue' all describe the same constraint: memory, not logic, now sets the price of intelligence.
The Memory Cartel's Five-Year Bet: Why DRAM Is the New Oil
SK hynix's plan to double wafer capacity by 2031 confirms what Intel and Qualcomm are saying out loud — HBM has drained the commodity memory pool, and the bill is landing on every device below the AI rack.
The Memory Wall Is Now the Cost Wall
Why HBM, DRAM, and the storage stack — not GPUs — are the binding constraint on the AI buildout, and what unbinds them.
Signal Briefing: May 27, 2026
SK Hynix embeds cooling inside the HBM stack while Taiwan arrests expose active Nvidia chip smuggling routes — a day that maps the stress fractures in AI compute supply.
When Memory Starts Cooling Itself: HBM's Thermal Wall Becomes a Supply Chain Story
SK Hynix is moving liquid cooling inside the memory stack — a sign that the AI compute bottleneck is migrating from bandwidth to heat, and that the HBM duopoly is about to get even narrower.
The Memory Wall: Why Bandwidth — Not Compute — Is the Binding Constraint in AI Hardware
The AI industry spent three years obsessing over compute. The bottleneck that actually determines inference economics is memory bandwidth, and the implications reshape the entire semiconductor landscape.