Google's Intel TPU Deal Signals the End of CoWoS Monopoly

The single most consequential AI-infrastructure story of the week is not a gigawatt announcement or a model launch. It is a procurement document. Google has reportedly booked Intel to package more than three million TPUs in 2028, and SK hynix is qualifying Intel’s EMIB process for HBM integration (Tom’s Hardware). That sentence — quietly disclosed, easily missed — is the first credible breach of the CoWoS monopoly that has defined the economics of frontier AI hardware since 2023.

For two years the binding constraint on AI compute has not been wafers. It has been the silicon interposer that stitches a logic die to its stack of HBM. TSMC’s CoWoS line has rationed Nvidia’s, Google’s, AMD’s, Amazon’s, and Microsoft’s accelerators on the same allocation calendar. When the entire industry queues at one packaging house, the queue is the market. Breaking that queue — even partially — changes how the next leg of the buildout gets financed, priced, and dimensioned.

The bottleneck nobody could route around

The shape of the constraint is now well-understood. A modern AI accelerator is not really a chip; it is a substrate-scale assembly. The logic die sits on a silicon interposer alongside six to eight HBM3E or HBM4 stacks, all connected by micro-bumps at densities a conventional organic package cannot achieve. TSMC’s CoWoS-S (silicon-on-substrate) and the newer CoWoS-L (with localized silicon bridges) are the only processes shipping at the volume, yield, and bump pitch that frontier accelerators require.

TSMC’s own roadmap, laid out in its latest fab-expansion analysis, is to roughly double CoWoS capacity each year through 2027, with multi-fab N2 ramps and SoIC (3D stacking) coming online in parallel. The numbers are aggressive — but they have been aggressive every year since 2023, and demand has outrun them every year. TSMC’s most recent disclosures point to mid-five-figure wafer-equivalents per month by end-2026, against orders that imply triple that if every accelerator program shipped its declared volume. CoWoS has been the most leveraged line in the entire semiconductor supply chain: a single fire, a single yield excursion at one of two AP6/AP7 buildings in Chunan or Zhunan, and Nvidia’s quarter slips.

What everyone in the industry has wanted — and what nobody has been able to qualify at scale — is a second source.

Why Intel, why now

Intel’s Foveros and EMIB technologies have existed for years; they ship inside Meteor Lake, Lunar Lake, and Ponte Vecchio. EMIB, in particular, has a structural advantage worth understanding: rather than placing the entire die complex on a giant, expensive silicon interposer, EMIB uses small silicon “bridges” embedded into an organic substrate, connecting only the bits that need high-density interconnect (logic-to-HBM, primarily). It is cheaper per assembled unit and avoids the reticle-limit gymnastics that CoWoS-L is increasingly forced into for 3.5- and 4-reticle designs.

The problem with EMIB has never been the physics. It has been the customers. Intel’s Foundry Services has never had a hyperscaler willing to put a flagship accelerator program on its packaging line at volume. Google reportedly committing more than three million TPU units for 2028 — and SK hynix qualifying HBM placement on EMIB — closes both halves of that loop. Google has the patience and internal silicon team to absorb the qualification risk; SK hynix has the HBM volumes to make a second packaging path commercially worthwhile to support.

Three million TPUs is a meaningful number. For context, the TPU v5/v6 generations have been estimated (from disclosed Google capex run-rates and public power filings) in the low-to-mid hundreds of thousands of units per year. A 2028 plan in the millions implies both a v7-class part and a doubling-or-more of Google’s internal accelerator deployment versus today — and an explicit decision not to put all of that growth on TSMC AP7.

The competitive cascade

Why does one customer matter so much? Because advanced packaging is a process with extreme learning-curve effects. Yields improve sharply with cumulative volume; tool-supplier roadmaps follow committed demand; HBM vendors only invest in qualifying alternate flows when there is a paying customer at the other end. A single hyperscaler-scale commitment turns Intel’s packaging line from a science project into a credible second source — which means the next customer faces a much lower switching cost.

The likely cascade: AWS Trainium, which has been a relatively early CoWoS adopter and has the most aggressive internal-silicon ambitions outside Google, is the obvious next candidate. Microsoft’s Maia line is on a similar trajectory. Even Nvidia, which has stuck to TSMC packaging out of pure pragmatism, gains optionality — and pricing leverage — the moment a credible alternative exists at hyperscaler volume. AMD’s announcement this week that its 256-core “Venice” EPYC outperforms Nvidia’s Vera by 3.3x at rack level (Tom’s Hardware) is the kind of claim that only becomes interesting if AMD can actually package and ship the volumes — and Intel’s EMIB capacity, if proven, becomes available to AMD too.

The price implications are not subtle. TSMC has been able to capture roughly half of the cost premium of a modern accelerator package because it has been the only viable supplier. Industry analysts have estimated CoWoS-L gross margins north of 60% — well above TSMC’s blended foundry margin. A credible second source compresses that premium, which translates either into lower system prices for hyperscalers (good for inference unit economics) or into higher margins for the accelerator designer (good for Nvidia, AMD, and the in-house silicon teams). Either way, the share of system cost going to packaging stops growing.

The HBM angle

The other half of the news — SK hynix testing Intel’s EMIB for HBM integration — deserves separate weight. HBM is the second great chokepoint of the AI buildout, with Samsung, SK hynix, and Micron tripling capex into HBM3E and HBM4 lines through 2027. The constraint there has been not just capacity but qualification: each HBM vendor has to certify its stack against each packaging flow, which is a multi-quarter process involving thermal, mechanical, and electrical signoff.

SK hynix qualifying EMIB does two things. First, it gives Intel’s packaging line a real HBM supply path — without HBM qualification, EMIB-packaged accelerators are non-functional regardless of how good the bridges are. Second, it gives SK hynix optionality on which packaging house it ships to, which marginally reduces its own concentration risk to TSMC’s allocation decisions. Micron, which has been the late entrant in HBM3E, has obvious incentive to follow.

The steelman: this is mostly a 2028 story

The honest counter-framing is that three million packaged units in 2028 is roughly two and a half years away. Intel Foundry has missed timelines before. EMIB at hyperscaler-grade yields, with HBM4 attached at advertised speeds, has not been demonstrated at the volume Google needs. Lip-Bu Tan’s Intel is still mid-restructuring. The history of “second source for TSMC” announcements — Samsung Foundry’s repeated runs at 3nm leading-edge customers, GlobalFoundries’ high-NA EUV deferrals — is a graveyard of credible-sounding deals that did not ship.

There is also a more cynical reading: that Google is using the Intel commitment primarily as leverage against TSMC’s allocation and pricing for 2026-27, and the actual 2028 volumes will be renegotiated downward once TSMC offers concessions. This is how procurement works at hyperscaler scale, and it would not be the first time. If you believe this framing, the news is real but its operational consequences are smaller — TSMC remains the structural winner, and Intel gets a marketing reference customer rather than a market.

The strongest version of the bear case rests on simple capacity math: even if Intel ramps EMIB aggressively, its packaging output through 2028 is unlikely to exceed mid-single-digit percent of TSMC’s CoWoS capacity. CoWoS remains the marginal supplier for the industry as a whole, which means CoWoS still sets the price.

I find this counter-framing partially convincing but ultimately underweight. The reason: in a constrained market, the marginal supplier sets the price, but the second source sets the expectation. Once buyers know a real alternative exists at any volume, TSMC loses the ability to extract monopoly rents on the increment. And monopoly rents on the increment are most of what CoWoS-L margins have been.

What the broader feed says about the timing

Two adjacent stories make this development more consequential than it would otherwise be. First, China’s reported drafting of a $295 billion plan for a national AI data-center grid running on 80% domestic chips by 2028. SMIC and CXMT cannot match leading-edge logic or HBM, but they do not need to: a parallel Chinese stack with its own packaging capacity (likely JCET-led) further fragments the global packaging landscape and reduces the share of frontier AI compute riding on a single Taiwanese supplier.

Second, The Register’s reporting on the 2030 power wall — that grid operators in PJM, ERCOT, and the major European interconnects are increasingly unable to honor data-center interconnection queues — suggests the binding constraint on the AI buildout is shifting from silicon to electrons. If silicon is genuinely going to be less constrained by 2028, then the marginal datacenter built that year will be limited by megawatts, not by accelerators. That changes which side of the trade has pricing power.

These three threads — a credible second packaging source, a parallel Chinese stack, and a tightening power constraint — point at the same structural conclusion. The accelerator scarcity premium that has defined hyperscaler economics from 2023 through 2025 is being arbitraged away. The next premium will sit somewhere else.

What to watch

A few specific signals will tell us whether the Google-Intel deal is real or theatrical. First: the next Intel Foundry earnings call. If management confirms a hyperscaler-scale advanced-packaging commitment with reservation revenue tied to it, the deal is real; if it remains “in discussion,” lower your conviction. Second: SK hynix’s HBM qualification disclosures — specifically whether EMIB shows up alongside CoWoS in their next quarterly material. Third: TSMC’s own CoWoS pricing in 2026 contract negotiations. If TSMC concedes on pricing or shortens its allocation horizons, that is the clearest signal that the second-source threat is biting.

Beyond the deal itself, the more interesting watch is whether Arista’s 1.6T AI-fabric switch announcement and the broader scale-out networking buildout become the new bottleneck. As packaging and HBM ease, the next ratio that matters is interconnect bandwidth per packaged accelerator. The constraint moves; it does not disappear.

The pattern across the last three years of the AI buildout has been a rolling chokepoint: leading-edge wafers (2022), HBM (2023), CoWoS (2024-25), power (2026-27), and most likely networking and cooling thereafter. Each transition has re-priced the equity of the supplier holding the bottleneck and the customer paying the toll. The Google-Intel deal is the first major signal that the CoWoS toll booth — the most lucrative in the chain — is finally getting a competitor.

That is worth more than a headline.