Packaging Is the New Process Node: Why CoWoS Still Gates the AI Buildout

The story of AI compute over the past three years has been routinely told as a story about transistors — Hopper, Blackwell, MI300X, TPU v5, the cadence of process-node shrinks at TSMC. That framing is wrong, or at least dangerously incomplete. The binding constraint on how many frontier accelerators the world can ship in 2026 is not 3nm wafer starts. It is the area of silicon interposer that TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) lines can produce, and the HBM stacks that bond onto it. This week, TSMC made that constraint a little more visible — and a little more durable.

The disclosure beneath the headline

At Computex-adjacent briefings, TSMC’s senior VP Kevin Zhang told reporters that panel-level packaging (PLP) — and TSMC’s own CoPoS (Chip-on-Panel-on-Substrate) variant in development — will not replace wafer-level CoWoS “anytime soon” for the largest AI processors. Wafer-level packaging, he said, remains “considerably more advanced,” and CoWoS can already scale to a single package containing up to 58 dies (Tom’s Hardware).

To a casual reader this looks like a vendor reassuring customers that their existing technology has runway. Read more carefully it is something stronger: TSMC is telling Nvidia, AMD, Broadcom, Marvell, Amazon, Google, Microsoft, and Meta that the supply-chain workaround many of them have been quietly funding — switching the highest-volume AI parts to a rectangular glass or organic panel format, which would dramatically expand throughput and reduce dependence on 300mm wafer interposer real estate — is not coming on a timeline that affects 2026 or 2027 product economics. CoWoS remains the gate. And CoWoS capacity, as TSMC has discussed in its own earnings disclosures, has roughly doubled year over year through 2025 and is on track for another large step in 2026, yet still is sold out years forward.

The thesis: the AI infrastructure industry has spent the last 18 months optimizing every other variable — power purchase agreements, liquid cooling retrofits, optical interconnect, even rural land deals — because the one variable it cannot accelerate is the rate at which large interposers and HBM-stacked accelerators come off TSMC’s back-end lines. This week’s news is a reminder that the workaround is not arriving on schedule.

Why packaging is the actual bottleneck

A modern AI accelerator is not a chip. It is a small printed-circuit-style assembly: one or more compute dies (often multi-tile, as Intel’s resurfaced “Arctic Sound” prototype reminded us is hardly new — that cancelled Xe-HP part already sported two tiles and 32GB of HBM2E, as a Tom’s Hardware writeup of an engineering sample showed this week), surrounded by four to eight HBM stacks, all sitting on a silicon interposer that routes the tens of thousands of fine-pitch connections required to keep memory bandwidth up to compute throughput.

Each of those elements has its own constraint:

• Logic dies: TSMC N3/N3E and increasingly N2. Constrained, but expandable.
• HBM stacks: SK Hynix dominant, Samsung catching up, Micron a third source. Disclosed in earnings to be sold out through 2026 and into 2027.
• Interposer area: This is the choke. CoWoS today uses a silicon interposer fabricated on its own 65nm-class line, and the maximum reticle field is a hard physical ceiling. CoWoS-L stitches multiple interposers together; this is how Blackwell and its successors get larger, and how TSMC reaches the “58 dies in one package” headline.
• Advanced substrate: ABF substrate from Ibiden, Unimicron, AT&S. Also tight.

CoWoS is the single point where all of these have to come together with sub-micron alignment, vertical via integrity, and yields that justify a $30,000–$50,000 accelerator. Doubling wafer-fab capacity at the front end does nothing if back-end packaging can’t keep pace. This is what makes Zhang’s comment load-bearing. Panel-level packaging — where the substrate is a 600mm × 600mm rectangle rather than a 300mm round wafer — would, in principle, deliver something like 3–5× the usable substrate area per processing step, plus the ability to escape reticle limits with different stitching topologies. If CoPoS or a competitor (Samsung, Powertech, ASE, Amkor all have panel programs) were ready for the highest-end parts in 2027, the supply curve would bend sharply. TSMC is signaling it will not.

The downstream evidence that everyone is routing around the same constraint

If packaging were not the binding constraint, you would not see the rest of this week’s news look the way it does.

AMD’s MEXT acquisition. AMD this week took over MEXT, a memory-tiering startup whose Predictive Memory Engine lets NAND appear as DRAM to applications by intelligently prefetching pages between tiers (Tom’s Hardware). The framing — “address growing memory constraints in the data center” — is polite phrasing for: HBM is rationed, DDR5 channels are saturated, and CXL deployments have been slower than predicted. A software-and-controller approach to extend the effective DRAM working set with flash is exactly the kind of margin-mining work you do when you cannot simply buy more HBM. It also suggests that for inference workloads — where many parameters are touched infrequently — there is real room to substitute cheap NAND for expensive packaged DRAM. That, in turn, partly relieves the HBM-packaging chokepoint, but only for workloads that tolerate the tiering latency.

The new server sockets. AMD’s SP7 socket for EPYC “Venice” and Intel’s LGA9324 socket for “Diamond Rapids” both surfaced at Computex with 16 DDR5 memory channels — twice today’s typical count (Tom’s Hardware). These are physically enormous; the LGA9324 is, as the name implies, a 9,324-pin socket. The chase here is bandwidth and capacity to feed CPU-side workloads — including the host portion of disaggregated inference and the orchestration layers around GPU clusters — without resorting to scarce HBM. When you see 16 DDR5 channels appear in a CPU socket, you are seeing the cost of an HBM shortage being paid by the CPU pin-count, the motherboard real-estate, and the cooling envelope.

Marvell’s optically-connected data center. Also this week, Marvell described interconnects sampling later in 2026 that would optically connect data centers across hundreds to thousands of kilometers, allowing CSPs to “pool resources based on workload” (Tom’s Hardware). The technical pitch is about flexibility; the commercial pitch is about not stranding accelerators. If your CoWoS allocation produced 200,000 GPUs in cluster A and the demand is in cluster B, the cheapest way to use the asset is to lay glass between the two and reorganize the abstraction. You only invest in this if the assets being pooled are individually scarce and individually expensive. The relevant constraint here, again, lives upstream at TSMC’s packaging lines.

This is what a single bottleneck looks like as it propagates through a $400B annual capex cycle: in motherboard sockets that grow grotesquely, in memory-tiering startups getting acquired, in cross-continental optical fabrics, in custom silicon programs at every hyperscaler attempting to get their own queue position with TSMC’s back end.

The counter-argument: the constraint is loosening, not tightening

The honest steelman against this framing has three parts.

First, capacity is being added aggressively. TSMC has publicly committed to roughly doubling CoWoS capacity again in 2026 versus 2025, and is shifting some advanced packaging to its Arizona and Japan footprints. ASE, Amkor, and SPIL are scaling their own equivalent flows. Samsung’s I-Cube and Intel Foundry’s EMIB-T add real alternative capacity for parts that do not strictly require TSMC. By late 2027 there will be meaningfully more packaging supply than today, and Zhang’s “not anytime soon” should be read as “not in 2027,” not “not ever.”

Second, the workload mix is shifting. As inference dominates the deployed footprint, the marginal accelerator does not necessarily need eight HBM3E stacks. AMD’s MEXT move points at exactly this — for many serving workloads, slower-but-cheaper memory tiers are economically rational. Anthropic’s reported willingness to verify user IDs and Anthropic’s continued hiring around supply chain (Meta’s Sham Parmar joined Anthropic this week to focus on power and cooling, per DCD) both suggest model providers are planning for inference economics that do not require ever-larger HBM budgets per query. If inference unit economics improve through software (KV-cache management, the kind of work the CacheWise arXiv paper this week describes for coding agents) and through tiered memory, then accelerator demand per dollar of revenue softens, and packaging stops being the gate.

Third, the gating could move upstream. HBM yields and stack heights are themselves limiting. If SK Hynix and Samsung get to 16-high stacks on schedule and Micron’s HBM4 ramps, the per-package memory capacity rises enough that fewer packages are needed for a given parameter count. The bottleneck may simply slide from interposer area to HBM die.

Each of these is real. But none of them is a 2026 story. The 2026 story is the one Zhang told this week: the workaround is not ready, the existing lines are sold out, and the rest of the supply chain is paying around it.

What to watch

A few specific signals over the next two quarters will tell you whether this framing is correct or whether the constraint is loosening faster than the public disclosures imply.

1. TSMC’s quarterly CoWoS guidance language. Watch the July and October earnings calls. If TSMC raises 2026 packaging capacity guidance again — they’ve raised it multiple times in the recent cycle — it tells you demand is still outrunning supply. If they hold flat, it may mean the demand curve is finally inflecting downward, consistent with the inference-economics steelman.

2. HBM contract pricing. SK Hynix and Micron disclose long-term contract structures in their quarterlies. If contract pricing for HBM3E and HBM4 stays at premium levels and 2027 allocation discussions are still happening in mid-2026, packaging and memory remain the gate. A softening here would be the first quantitative sign that AMD’s MEXT-style tiering and software cache optimizations are biting.

3. Hyperscaler custom-silicon timelines. Amazon’s Trainium, Google’s TPU, Microsoft’s Maia, and Meta’s MTIA all need CoWoS or equivalent. Slippage in their published timelines is more informative than slippage in Nvidia’s, because the hyperscalers have less ability to jump the TSMC queue. Watch for delays disclosed at re:Invent and Google Cloud Next.

4. Substrate suppliers. Ibiden’s and Unimicron’s quarterly volume and capex disclosures are the canary for whether the secondary chokepoint — ABF substrate — is itself binding. If they keep guiding capacity expansions, advanced packaging stays the rate-limiter through 2027.

5. Panel-level packaging milestones. Samsung, ASE, and Powertech have all guided to 2027–2028 production for panel-level for high-end logic. If any of them pulls in a milestone — first qualified customer, first HVM tape-in — the timing of the inflection moves. Zhang’s comment this week suggests TSMC does not believe this is imminent.

The temptation, in writing about AI infrastructure, is to lead with the megawatt and the megadollar numbers. Project Jupiter in New Mexico, Project Taurus in Colorado, Amazon’s multibillion-dollar Missouri buildout — all of these landed in the feed this week. They matter, but they are downstream. Power agreements, water permits, county-level moratoriums, and grid-support obligations are all responses to demand for AI compute. The supply of that compute is rate-limited by a few thousand square meters of clean-room floor in Hsinchu and a handful of HBM lines in Icheon and Boise. Until panel-level packaging actually displaces wafer-level — and TSMC this week told the market that day is not soon — every other constraint is downstream of that one. The whole industry is currently optimizing around a packaging step, and pretending otherwise misreads where the leverage lives.