Signal Briefing: June 11, 2026

China Drafts $295B National AI Data Center Grid on 80% Domestic Silicon

China is finalizing a plan to spend roughly 2 trillion yuan (~$295B) over five years on a nationwide AI data center grid, with a stated target of running 80% on domestically produced silicon, according to Tom’s Hardware. The projected 2028 completion timeline is aggressive given current limits on domestic chip production at advanced nodes.

Why this matters. At roughly $60B/year, this would make China’s state-directed AI infrastructure program broadly comparable in annual run rate to individual US hyperscaler capex cycles (per FY24-25 10-K disclosures). The 80% domestic chip mandate is the real structural signal: it creates a committed demand floor for SMIC and Huawei Ascend production regardless of export-control outcomes, and it materially limits the total addressable market for NVIDIA and AMD in the world’s second-largest compute market.

Confidence: medium — single trade report on a draft plan; figures and timeline have not been confirmed by primary government disclosure.

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Google Books Intel for 3M+ TPU Packages in 2028, Testing EMIB for HBM

Google has placed an order for Intel to assemble more than 3 million TPUs in 2028 following successful testing of Intel’s EMIB advanced packaging for HBM integration, per Tom’s Hardware. SK Hynix is reported to be involved in the HBM validation work alongside Intel’s packaging line.

Why this matters. This is the clearest evidence yet that Google is treating advanced packaging capacity as a supply-chain risk to be distributed — pulling Intel’s EMIB into the TPU stack reduces dependence on TSMC’s CoWoS, which remains the primary bottleneck for AI accelerator production across the industry. For Intel, a 3M-unit foundry commitment at this scale is a meaningful revenue and credibility anchor for its IFS business at exactly the moment it needs design wins.

Confidence: medium — sourced from a single trade report; Google and Intel have not made a primary disclosure.

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TSMC Executing Largest Fab Expansion in Semiconductor History

A detailed analysis at Tom’s Hardware documents TSMC simultaneously ramping N2 across multiple fabs while massively expanding CoWoS and SoIC advanced packaging capacity to address the AI accelerator bottleneck. The piece describes the buildout as the largest manufacturing expansion in semiconductor industry history.

Why this matters. CoWoS has been the single hardest constraint on how fast GPU and TPU production can scale — TSMC’s concurrent packaging expansion is what ultimately sets the ceiling for how many AI accelerators ship in 2026-2028. The N2 ramp matters for future-generation efficiency, but the packaging capacity unlock is what determines near-term supply for H100/B200-class and successor chips. Any slip in this ramp propagates directly into hyperscaler capex deployment timelines.

Confidence: high — detailed analyst-level coverage of disclosed fab plans; consistent with TSMC investor day and capex guidance on record.

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Data Center Growth May Hit a Power Wall by 2030

Grid operators are on track to struggle to support continued hyperscale data center construction beyond 2030, according to analysis at The Register. The piece frames the constraint as a structural one: transmission infrastructure buildout timelines are measured in years to decades, while AI-driven demand growth is running on a two-to-three year product cycle.

Why this matters. The “power wall” is increasingly the binding constraint in infrastructure planning, not silicon supply or capex availability. The responses already visible in the feed — floating data centers (Samsung/Supermicro), tent deployments (Meta), sodium-ion grid storage (GM/Peak Energy), and microgrid-as-prime-power architectures — are all symptoms of operators trying to get around interconnection queues that in many markets now run three to seven years. Where you can site a data center is becoming as strategically important as what chips you run inside it.

Confidence: high — consistent with publicly reported grid interconnection queue data from MISO, PJM, and CAISO across 2024-2026.

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Brussels’ Data Center Efficiency Scorecard Could Trigger Credit Downgrades

The EU’s proposed A-to-G energy efficiency grading system for data centers may carry a financing sting: Moody’s has indicated that poor scores could affect credit ratings for affected operators, per The Register. The scorecard is part of Brussels’ broader effort to impose accountability on the sector’s rapidly growing energy footprint.

Why this matters. Regulatory risk has historically been a second-order concern in data center capex planning — power procurement and land costs dominate. A Moody’s linkage between efficiency grades and borrowing costs would change the math directly, particularly for the wave of merchant and co-location operators financing new European capacity into a high-rate environment. Hyperscalers with investment-grade balance sheets absorb this more easily; the pressure falls hardest on the mid-tier operators building out to serve AI inference demand.

Confidence: medium — Moody’s commentary is cited but the scorecard itself is still a proposal; final regulatory form and enforcement timeline are not yet set.